Type of Document Master's Thesis Author Priya, Kanu Author's Email Address firstname.lastname@example.org URN etd-08222011-133618 Title Study of Physical Unclonable Functions at Low Voltage on FPGA Degree Master of Science Department Electrical and Computer Engineering Advisory Committee
Advisor Name Title Nazhandali, Leyla Committee Chair Schaumont, Patrick Robert Committee Member Tront, Joseph G. Committee Member Keywords
- Low Power
- Physical Unclonable Functions
- Ring Oscillator
- Process Variation
Date of Defense 2011-07-22 Availability unrestricted AbstractPhysical Unclonable Functions (PUFs) provide a secure, power efficient and non-volatile means of chip identification. These are analogous to one-way functions that are easy to create but impossible to duplicate. They offer solutions to many of the FPGA (Field Programmable Gate Array) issues like intellectual property, chip authentication, cryptographic key generation and trusted computing. Moreover, FPGA evolving as an important platform for flexible logic circuit, present an attractive medium for PUF implementation to ensure its security.
In this thesis, we explore the behavior of RO-PUF (Ring Oscillator Physical Unclonable Functions) on FPGA when subjected to low voltages. We investigate its stability by applying environmental variations, such as temperature changes to characterize its effectiveness. It is shown with the help of experiment results that the spread of frequencies of ROs widens with lowering of voltage and stability is expected. However, due to inherent circuit challenges of FPGA at low voltage, RO-PUF fails to generate a stable response. It is observed that more number of RO frequency crossover and counter value fluctuation at low voltage, lead to instability in PUF. We also explore different architectural components of FPGA to explain the unstable nature of RO-PUF. It is reasoned out that FPGA does not sustain data at low voltage giving out unreliable data. Thus a low voltage FPGA is required to verify the stability of RO-PUF. To emphasize our case, we look into the low power applications research being done on FPGA. We conclude that FPGA, though flexible, being power inefficient, requires optimization on architectural and circuit level to generate stable responses at low voltages.
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