Type of Document Dissertation Author Lehne, Mark Author's Email Address firstname.lastname@example.org URN etd-08282008-225723 Title An Analog/Mixed Signal FFT Processor for Ultra-Wideband OFDM Wireless Transceivers Degree PhD Department Electrical and Computer Engineering Advisory Committee
Advisor Name Title Raman, Sanjay Committee Chair Ellingson, Steven W. Committee Member Patterson, Cameron D. Committee Member Reed, Jeffrey Hugh Committee Member Tront, Joseph G. Committee Member Woodall, William H. Committee Member Keywords
- FFT Processor
- Mixed Signal
Date of Defense 2008-07-28 Availability unrestricted AbstractAs Orthogonal Frequency Division Multiplexing (OFDM) becomes more prevalent in
new leading-edge data rate systems processing spectral bandwidths beyond 1 GHz, the
required operating speed of the baseband signal processing, specifically the Analog-
to-Digital Converter (ADC) and Fast Fourier Transform (FFT) processor, presents
significant circuit design challenges and consumes considerable power. Additionally,
since Ultra-WideBand (UWB) systems operate in an increasingly crowded wireless
environment at low power levels, the ability to tolerate large blocking signals is critical.
The goals of this work are to reduce the disproportionately high power consumption
found in UWB OFDM receivers while increasing the receiver linearity to better handle
To achieve these goals, an alternate receiver architecture utilizing a new FFT processor is proposed. The new architecture reduces the volume of information passed
through the ADC by moving the FFT processor from the digital signal processing
(DSP) domain to the discrete time signal processing domain. Doing so offers a reduction in the required ADC bit resolution and increases the overall dynamic range of the UWB OFDM receiver.
To explore design trade-offs for the new discrete time (DT) FFT processor, system
simulations based on behavioral models of the key functions required for the processor
are presented. A new behavioral model of the linear transconductor is introduced
to better capture non-idealities and mismatches. The non-idealities of the linear
transconductor, the largest contributor of distortion in the processor, are individually
varied to determine their sensitivity upon the overall dynamic range of the DT FFT
processor. Using these behavioral models, the proposed architecture is validated and
guidelines for the circuit design of individual signal processing functions are presented.
These results indicate that the DT FFT does not require a high degree of linearity
from the linear transconductors or other signal processing functions used in its design.
Based on the results of the system simulations, a prototype 8-point DT FFT processor is designed in 130 nm CMOS. The circuit design and layout of each of the circuit
functions; serial-to-parallel converter, FFT signal flow graph, and clock generation
circuitry is presented. Subsequently, measured results from the first proof-of-concept
IC are presented. The measured results show that the architecture performs the
FFT required for OFDM demodulation with increased linearity, dynamic range and
blocker handling capability while simultaneously reducing overall receiver power consumption. The results demonstrate a dynamic range of 49 dB versus 36 dB for the
equivalent all-digital signal processing approach. This improvement in dynamic range
increases receiver performance by allowing detection of weak sub-channels attenuated
by multipath. The measurements also demonstrate that the processor rejects large
narrow-band blockers, while maintaining greater than 40 dB of dynamic range. The
processor enables a 10x reduction in power consumption compared to the equivalent
all digital processor, as it consumes only 25 mWatts and reduces the required ADC bit
depth by four bits, enabling application in hand-held devices.
Following the success of the first proof-of-concept IC, a second prototype is designed to
incorporate additional functionality and further demonstrate the concept. The second
proof-of-concept contains an improved version of the serial-to-parallel converter and
clock generation circuitry with the additional function of an equalizer and parallel-
Based on the success of system level behavioral simulations, and improved power
consumption and dynamic range measurements from the proof-of-concept IC, this
work represents a contribution in the architectural development and circuit design of
UWB OFDM receivers. Furthermore, because this work demonstrates the feasibility
of discrete time signal processing techniques at 1 GSps, it serves as a foundation that
can be used for reducing power consumption and improving performance in a variety
of future RF/mixed-signal systems.
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