Type of Document Dissertation Author Blumer, Aric David Author's Email Address email@example.com URN etd-10262007-144416 Title Register Transfer Level Simulation Acceleration via Hardware/Software Process Migration Degree PhD Department Electrical and Computer Engineering Advisory Committee
Advisor Name Title Patterson, Cameron D. Committee Chair Athanas, Peter M. Committee Member Broadwater, Robert P. Committee Member Jones, Mark T. Committee Member Mortveit, Henning S. Committee Member Keywords
- RTL Simulation
- Process Migration
- Run-time Reconfiguration
- Reconfigurable Computing
- Formal Modeling
- Canonical RTL
- Executive Locality of Reference
Date of Defense 2007-10-15 Availability unrestricted AbstractThe run-time reconfiguration of Field Programmable Gate Arrays (FPGAs) opens new
avenues to hardware reuse. Through the use of process migration between hardware and
software, an FPGA provides a parallel execution cache. Busy processes can be migrated into
hardware-based, parallel processors, and idle processes can be migrated out increasing the
utilization of the hardware. The application of hardware/software process migration to the
acceleration of Register Transfer Level (RTL) circuit simulation is developed and analyzed.
RTL code can exhibit a form of locality of reference such that executing processes tend to be
executed again. This property is termed executive temporal locality, and it can be exploited by
migration systems to accelerate RTL simulation.
In this dissertation, process migration is first formally modeled using Finite State Machines
(FSMs). Upon FSMs are built programs, processes, migration realms, and the migration
of process state within a realm. From this model, a taxonomy of migration realms is
developed. Second, process migration is applied to the RTL simulation of digital circuits. The
canonical form of an RTL process is defined, and transformations of HDL code are justified
and demonstrated. These transformations allow a simulator to identify basic active units within
the simulation and combine them to balance the load across a set of processors. Through the
use of input monitors, executive locality of reference is identified and demonstrated on a set
of six RTL designs. Finally, the implementation of a migration system is described which
utilizes Virtual Machines (VMs) and Real Machines (RMs) in existing FPGAs. Empirical and
algorithmic models are developed from the data collected from the implementation to evaluate
the effect of optimizations and migration algorithms.
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