Title page for ETD etd-11198-212219

Type of Document Master's Thesis
Author Walters, Allison L.
Author's Email Address awal@erols.com
URN etd-11198-212219
Title A Scaleable FIR Filter Implementation Using 32-bit Floating-Point Complex Arithmetic on a FPGA Base Custom Computing Platform
Degree Master of Science
Department Electrical Engineering
Advisory Committee
Advisor Name Title
Athanas, Peter M. Committee Chair
Davis, Nathaniel J. IV Committee Member
Jones, Mark T. Committee Member
  • reconfigurable computing
  • digital signal processing
  • FIR filters
Date of Defense 1998-01-30
Availability unrestricted
This thesis presents a linear phase finite impulse response filter implementation developed on a custom computing platform called WILDFORCE. The work has been motivated by ways to off-load intensive computing tasks to hardware for indoor communications channel modeling. The design entails complex convolution filters with customized lengths that can support channel impulse response profiles generated by SIRCIM. The paper details the partitioning for a fully pipelined convolution algorithm onto field programmable gate arrays through VHDL synthesis. Using WILDFORCE, the filter can achieve calculations at 160 MFLOPs/s.

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