Type of Document Master's Thesis Author Varma, Anup URN etd-12172001-152439 Title Modeling and Synthesis with SystemC Degree Master of Science Department Electrical and Computer Engineering Advisory Committee
Advisor Name Title Armstrong, James R. Committee Chair Baker, James M. Jr. Committee Member Gray, Festus Gail Committee Member Keywords
Date of Defense 2001-12-13 Availability unrestricted AbstractWith the increasing complexity of Application Specific Integrated Circuits (ASICs), System-On-a-Chip (SoC) design seems to be the current chip design paradigm. Unlike ASICs, SoCs are a potpourri of diverse components, including general-purpose or special-purpose processors. Designing and testing these designs require a new methodology that supports system level modeling and hardware-software co-design. The Hardware Description Languages (HDLs) available today cannot meet this challenge.
SystemC is a new modeling language based on C++. Models written in SystemC are executable and do not dictate either hardware or software implementation. The model written in SystemC can be synthesized to hardware using the CoCentric SystemC Compiler (CCSC). Thus, the combination of SystemC and CCSC has the potential to be a powerful SoC design technique.
This thesis examines the usefulness of SystemC and CCSC to model and synthesize a GSM system. The encoders and decoders used in the GSM system are complex and represent challenging problems in the real world. The modeling methodology using SystemC is considered and the synthesis issues with CCSC are detailed. Simulation results using real sound samples and synthesis results are presented. Areas for future work are then outlined.
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