Type of Document Master's Thesis Author He, Yingchun Author's Email Address email@example.com URN etd-61798-172741 Title VLSI Implementation of a Run-time Configurable Computing Integrated Circuit - The Stallion Chip Degree Master of Science Department Electrical and Computer Engineering Advisory Committee
Advisor Name Title Athanas, Peter M. Committee Chair Jones, Mark T. Committee Member Tranter, William H. Committee Member Keywords
- run-time configurable computing
Date of Defense 1998-07-14 Availability unrestricted AbstractVLSI Implementation of a Run-time Configurable Computing Integrated Circuit The Stallion Chip
Reconfigurable computing architectures are gaining popularity as a replacement for general-purpose architectures for many high performance embedded applications. These machines support parallel computation and direct the data from the producers of an intermediate result to the consumers over custom pathways. The Wormhole Run-time Reconfigurable (RTR) computing architecture is a concept developed at Virginia Tech to address the weaknesses of contemporary FPGAs for configurable computing. The Stallion chip is a full-custom configurable computing "FPGA"-like integrated circuit with a coarse grained nature. Based on the result of the first generation device, the Colt chip, the Stallion chip is a follow-up configurable computing chip. This thesis focuses on the VLSI layout implementation of the Stallion chip. Effort has been made to explain many facts and advantages of the Wormhole Configurable Computing Machine (CCM). Design techniques, strategies, circuit characterization, performance estimation, and ways to solve problems when using CAD layout design tools are illustrated.
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